Best Papers
The Best Paper Award has been renamed, the ITC Ned Kornfield Best Paper Award in honor of Dr. Nathanial "Ned" Kornfield, ITC's founder and longtime Chairman Emeritus.
To encourage excellence in its technical program, ITC presents awards to authors of outstanding papers presented at ITC and published in the proceedings. In determining award-winning papers, the ITC Awards Selection Committee considers the quality of the papers as published in the Proceedings and as presented at the conference technical sessions. The committee's decisions are based on responses by conference attendees as recorded on session rating cards and on the observations and recommendations of the ITC Prrogram Committee.
| B = Best Paper, H = Honorable Mention | ||
| 1979 | B | Design
for Self-Verification: An Approach for Dealing with Testability Problems
in VLSI-Based Designs Richard Sedmak, Sperry Univac |
| 1980 | B | Soft
Error Testing, Tim May D.L. Crook, D.W. Gralian, R.A. Reininger, R.C. Smith, Intel Corp. |
| H | A
New Approach to High-Speed Codec Testing Matthew Mahoney, LTX Corp. |
|
| H | Testing
for Bipolar Integrated Circuit Failures Jayne Partridge, Charles Stark Draper Lab, Inc. |
|
| H | Electron
Beam Testing of Microprocessors G. Crichton, P. Fazekas and E. Wolfgang, Siemens AG (Germany) |
|
| 1981 | B | Automated
Measurement of 12- to 16-bit Converters Matthew Mahoney, LTX, Corp. |
| 1982 | B | Testability
Measures - What do they tell us? Vishwani Agrawal and M. Ray Mercer, AT&T Bell Laboratories |
| 1983 | B | Subnanosecond
Timing Measurements on MOS Devices Using Modern VLSI Test Systems Mark Barber, AT&T Bell Laboratories |
| H | HITEST
-- Intelligent Test Generation Gordon D. Robinson, Cirrus Computers, Ltd. |
|
| H | New
Techniques for High-Speed Analog Testing Matthew V. Mahoney, LTX Corp |
|
| 1984 | B | Random
Testing for Stuck-at-Storage Cells in an Embedded Memory William H. McAnney, Paul H. Bardell and Ved P. Gupta, IBM, Corp. |
| 1985 | B | The
Electrical Behavior of Gate-Oxide Short Defects Charles Hawkins, University of New Mexico, and Jerry Soden, Sandia National Laboratories |
| 1986 | B | Comparison
of Aliasing Errors for Primitive and Non-Primitive Polynomials T.W. Williams and C.W. Starke, IBM Corp., and W. Daehn and M. Gruetzner, University of Hannover |
| H | Reliability
and IC Electrical Properties of Gate Oxide Shorts Charles Hawkins, University of New Mexico, and Jerry Soden, Sandia National Laboratories |
|
| H | ISDN
Device Testing Demands A New Level of Performance from Automatic Test
Equipment R. Kramer, Teradyne, Inc. |
|
| 1987 | B | Hierarchical
Test Generation: Can AI Help? Balaji Krishnamurthy, Tektronix Labs |
| H | A
Generic Procedure for Evaluating VLSI Test System Timing Accuracy Marc Mydill, Texas Instruments, Inc. |
|
| 1988 | B | Membrane
Probe Card Technology - The Future for High-Performance Wafer Test Brian Leslie, Tencor Instruments, and Farid Matta, Hewlett-Packard Company |
| H | Test
Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for
a Gigahertz Production Test System Francois J. Henley and Hee-June Choi, Photon Dynamics, Inc. |
|
| H | Statistical
Delay Fault Coverage and Defect Level for Delay Faults E.S. Park and M. Ray Mercer, University of Texas at Austin, and Thomas W. Williams, IBM Corp. |
|
| 1989 | B | Built-in
Self-Test of the Macrolan Chip Richard Illman and Steve Clarke, ICL Mainframe Systems Division |
| H | A
High-Performance, 10-Volt Integrated Pin Electronics Driver Chris Branson, Tektronix, Inc. |
|
| H | A
250-MHz Shared-Resource VLSI Test System with High Pin-Count and Memory
Test Capability Shuji Kikuchi, Yoshihiko Hayashi, Takashi Matsumoto, Ryozou Yoshino and Ryuichi Takagi, Hitachi, Ltd. |
|
| 1990 | B | CMOS
Bridge Fault Detection Thomas M. Storey and Wojciech Maly, Carnegie Mellon University |
| H | Frequency
Enhancement of Digital Test Systems Leslie Ackner and Mark R. Barber, AT&T Bell Laboratories |
|
| H | Increased
CMOS Stuck-at Fault Coverage with Reduced IDDQ Test Sets Ronald R. Fritzmeier, Jerry M. Soden and R. Keith Treece, Sandia National Laboratories, and Charles F. Hawkins, University of New Mexico |
|
| 1991 | B | Implementing
1149.1 on CMOS Microprocessors William C. Bruce, Michael G. Gallup, Grady Giles and Tom Munns, Microprocessor and Memory Technology Group, Motorola, Inc. |
| H | The
Effect of Different Test Sets on Quality Level Prediction: When is 80%
Better Than 90%? Peter C. Maxwell, Robert C. Aitken, Vic Johansen and Inshen Chiang, Hewlett-Packard Company |
|
| 1992 | B | A
Comparison of Defect Models for Fault Location with IDDQ Measurements Robert C. Aitken, Hewlett-Packard Company |
| H | High-Performance
Pin Electronics with GaAs, A Contradiction in Terms? Ulrich Schoettmer and Holger Engelhard, Hewlett-Packard Company |
|
| H | A
Proposed Method of Accessing 1149.1 in a Backplane Environment Lee Whetsel, Texas Instruments, Inc. |
|
| 1993 | B | Structure
and Metrology for an Analog Testability Bus Kenneth P. Parker, John E. McDermid and Stig Oresjo, Hewlett-Packard Company |
| H | A
BIST Scheme for an SNR Test of a Sigma-Delta ADC M.F. Toner and G.W. Roberts, McGill University |
|
| 1994 | B | Defect
Classes - An Overdue Paradigm for CMOS IC Testing Charles F. Hawkins, Univ. of New Mexico; Jerry M. Soden and Alan W. Righter, Sandia National Labs; F. Joel Ferguson, Univ. of California, Santa Cruz |
| H | An
Analog Multi-Tone Signal Generator for Built-In Self Test A.K. Lu, G.W. Roberts, McGill University |
|
| 1995 | B | Improved
Boundary Scan Design Lee Whetsel, Texas Instruments, Inc. |
| H | Improving
DSP-Based Measurements with Spectral Interpolation Mark Burns, Texas Instruments, Inc. |
|
| 1996 | B | Weak-Write
Test Mode: an SRAM Cell Stability Design for Test Technique Ann Meixner, Jash Banik, Intel Corp. |
| H | Early
Capture for Boundary Scan Timing Measurments Keigh Loftstrom, KLIC Corp. |
|
| H | Process-Aggravated
Noise: New Validation and Test Problem Melvin Breuer, Sandeep Gupta, Univ. of Southern California |
|
| 1997 | B | Current
Signatures: Application Anne Gattiker, Wojciech Maly, Carnegie Mellon Univ. |
| H | Intrinsic
Leakage in Low-Power Deep-Submicron CMOS ICs Ali Keshvaritz, Intel Corp.; Kaushik Roy, Purdue Univ.; Charles Hawkins, Univ. of New Mexico |
|
| 1998 | B | Failure
Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods
Experiment Phil Nigh, Dave Vallett, Atul Patel, Jason Wright, IBM Microelectronics; Franco Motika, Donato Forlenza, Ray Kurtulik, Wendy Chong, Micrus Corporation |
| H | Defect
Detection with Transient Current Testing and its Potential for Deep Sub-micron
CMOS ICs Manoj Sachdev, Peter Janssen, Victor Zieren, Philips Research Laboratories |
|
| H | Probabilistic
Mixed-Model Fault Diagnosis David Lavo, Brian Chess, Tracy Larrabee, UC, Santa Cruz; Ismed Hartanto, Hewlett Packard Company |
|
| 1999 | B | "Current
Ratios: A Self-Scaling Technique for Production IDDQ Testing" Peter Maxwell, Pete O’Neill, Rob Aitken, Roland Dudley, Neal Jaarsma, Minh Quach, Don Wiseman; Hewlett-Packard |
| H |
"Logic
BIST for Large Industrial Designs: Real Issues and Case Studies" |
|
| H |
"BIST
for Phase-Locked Loops in Digital Applications" |
|
| H |
"The
Attack of the ‘Holey Shmoos’: A Case Study of Advanced DFD
and Picosecond Imaging Circuit Analysis (PICA)" |
|
| 2000 | B | "A
Stand-alone Integrated Test Core for Time and Frequency Domain Measurements" Gordon Roberts, Mohamed Hafed and Nazmy Abasharoun, McGill University |
| H | "Logic
Mapping on a Microprocessor" Hari Balachandran, Regy Thomas, John Carulli and Anjali Kinra, Texas Instruments |
|
| 2001 | B | "Neighbor Selection for Variance Reduction in IDDQ
and Other Parametric Data" R. Daasch, K. Cota and J. McNames, Portland State University; R. Madge, LSI Logic |
| H | "Debug Methodology for the McKinley Processor" D. Josephson and V. Govan, Hewlett-Packard; S. Poehlman, Intel |
|
| 2002 | B | "Architecting Millisecond Test Solutions for Wireless
Phone RFICs" John Ferrario, Steve Moss, Randy Wolf; IBM Microelectronics |
| H | "Complete, Contactless I/O Testing - Reaching the
Boundary in Minimizing Digital IC Testing Cost" Stephen Sunter and Benoit Nadeau-Dostie; LogicVision |
|
|
in honor of Dr. Kornfield, ITC's founder and longtime Chairman Emeritus |
||
| 2003 | B | "Elimination of Traditional Functional Testing of
Interface Timings at Intel" Mike Tripp, T.M. Mak and Anne Meixner; Intel Corporation |
| H | "Convolutional Compaction of Test Responses" Janusz Rajski and Chen Wang; Mentor Graphics, Jerzy Tyszer; Poznan University of Technology, and Sudhakar M. Reddy; University of Iowa |
|
| 2004 | B | "A New Probing Technique for High-Speed/High-Density Printed Circuit Boards" K. Parker, Agilent Technologies |
| H | "In Search of the Optimum Test Set-Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost" R. Madge, B. Benware, R. Turakhia, LSI Logic and R. Daasch, C. Schuermyer, J. Ruffler, Portland State University |
|
| H | "Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions" P. Nigh, A. Gattiker, IBM |
|
| 2005 | B | "Structural Tests for Jitter Tolerance in SerDes Receivers" Steve Sunter, Aubin Roy, LogicVision |
| 2006 | B | "Signature Based Diagnosis for Logic BIST" M. Sharma, W. Cheng, T. Rinderknecht, L. Lai and C. Hill, Mentor Graphics |