Test Week Tutorials

ITC 2015 Tutorials

ITC 2015 offers 12 tutorials, taught by leading experts, over two days. Catch up on the latest in an area with advanced tutorials or learn the basics. Tutorial titles appear below, click on a title for more details,


You can register for tutorials as part of the regular ITC registration on the ITC Registration Page.

Sunday Morning, October 4 Sunday Afternoon, October 4
1. Mixed-Signal DFT & BIST: Trends, Principles, and Solutions

Steve SUNTER

 

4. Practices in High Speed I/O Testing

Salem ABDENNADHER, Saghir SHAIKH
2. Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits Domenic FORTE, Mohammad TEHRANIPOOR 5. Testing of TSV-Based 2.5D- and 3D-Stacked ICs Erik Jan MARINISSEN
3. Beyond DFT: The Convergence of DFM, Variability, Yield, Test, Diagnosis and Reliability Srikanth VENKATARAMAN, Robert AITKEN  6. Delay Test: Concepts, Theory and Recent TrendsSuriyaprakash Natarajan and Arani Sinha
 
Monday Morning, October 5 Monday Afternoon, October 5
7. HIERARCHICAL TEST FOR TODAY’S SOC and IOTYervant ZORIAN  10. Memory Test & Repair in the Nanometer  Era Manuel D’ABREU, Yervant ZORIAN
8. TEST, DIAGNOSIS, AND ROOT-CAUSE IDENTIFICATION OF FAILURES FOR BOARDS AND SYSTEMS Krishnendu CHAKRABARTY, William EKLOW, Zoe CONROY  11. COMBINING STRUCTURAL AND FUNCTIONAL TEST APPROACHES ACROSS SYSTEM LEVELSArtur JUTMAN, Hans-Joachim WUNDERLICH, Matteo SONZA REORDA
9. STATISTICAL ADAPTIVE TEST METHODS TARGETINGZERO DEFECT” IC QUALITY AND RELIABILITY Adit SINGH 12. FROM DATA TO ACTIONS: APPLICATIONS OF DATA ANALYTICS IN SEMICONDUCTOR MANUFACTURING & TEST Haralampos STRATIGOPOULOS, Yiorgos MAKRIS

TUTORIAL SUMMARIES

  1. MIXED-SIGNAL DFT & BIST: TRENDS, PRINCIPLES, AND SOLUTIONS

    Stephen SUNTER


    We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing. Next, we discuss trends in ad hoc DFT and fault simulation, then all relevant IEEE DFT standards: 1149.1, .4, .6, .7, .8, P1149.10, and 1687. The trend analysis concludes with a review of BIST techniques. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, and last but not least, random analog. Next, seven essential principles of practical analog BIST are presented. Lastly, we discuss practical DFT techniques, ranging from analog defect simulation and the classic analog bus, to oversampling and undersampling methods that greatly improve range, resolution, and reusability.

    Intended Audience: Designers, DFT engineers, test engineers, and managers responsible for analog/mixed-signal/HSIO functions in SoCs

  2. TEST OPPORTUNITIES AND CHALLENGES FOR SECURE HARDWARE AND VERIFYING TRUST IN INTEGRATED CIRCUITS

    Domenic FORTE, Mohammad TEHRANIPOOR


    The migration from a vertical to horizontal business model has made it easier to introduce many vulnerabilities to electronic component design and supply chain. In the first part of this tutorial, we discuss the major issues that must be addressed including securing hardware, verifying trustworthiness of integrated circuits, unique key generation, side-channel attacks and more. . In the latter two parts of this tutorial, we will place more emphasis on detection and prevention of hardware Trojans and counterfeit electronic parts and discuss how test can help. In this tutorial, we will cover (i) An introduction to hardware security and trust (physically unclonable functions, true random number generation, hardware Trojans, counterfeit ICs, side-channel attacks, supply chain vulnerabilities, etc.), (ii) Background and motivation for hardware Trojan and counterfeit prevention/detection; (iii) Taxonomies related to both topics; (iv) Existing solutions; (v) Open test challenges; (vi) Design for security and trust, (vii) New and unified solutions to address these challenges.

    Intended Audience: This tutorial is perfect for either those who are beginners or those who have been involved in hardware security for several years. For beginners, we shall provide extensive motivation and background hardware security and trust. For the more experienced, we will discuss an up-to-date understanding of existing solutions, the challenges still unaddressed, and the role test and design for security plays in securing modern designs.

  3. BEYOND DFT: THE CONVERGENCE OF DFM, VARIABILITY, YIELD, TEST, DIAGNOSIS AND RELIABILITY

    Srikanth VENKATARAMAN, Robert AITKEN


    The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.

    Intended Audience: Test practitioners (DFT and product engineers, students, academics) who are interested in learning more about the interaction between design and test, as they relate to yield, manufacturability and variability, and how they affect chips in recent process technology; designers; yield, debug and FA engineers. Yield, fab metrology and DFM are covered at a basic-level to appeal to the typical test conference attendee while always relating to topics in test and diagnosis

  4. PRACTICES IN HIGH SPEED I/O TESTING

    Salem ABDENNADHER, Saghir SHAIKH


    This tutorial presents the existing industrial techniques to meet the ever increasing test complexity of High Speed IO’s (HSIO). It first describes the basic design of both serial and parallel HSIOs and then presents various testing methods of HSIO, such as timing margining, voltage margining, compensation testing, leakage testing and etc. The examples of all these test methods will be presented with special emphasis on DFT and BIST based approaches of HSIO testing and their suitability to the production level environment.

    Intended Audience: This tutorial is most suitable for design, test and DFT engineers involved in actual implementation of Hig Speed I/O based systems. The architects and engineering managers would also greatly benefit from this tutorial.

  5. TESTING OF TSV-BASED 2.5D- AND 3D-STACKED ICS

    Erik Jan MARINISSEN, Krishnendu CHAKRABARTY


    Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, testing for manufacturing defects remains an obstacle and potential showstopper before 3D-SICs can become a reality. There are concerns about the cost or, even worse, feasibility of testing such TSV-based 3D chips. In this tutorial, we present key concepts in 3D technology, terminology, and benefits. We discuss design and test challenges and emerging solutions for 2.5D- and 3D-SICs. Topics to be covered include an overview of 3D integration and trend-setting products such as a 2.5D-FPGA and 3D-stacked memory chips, test flows and test content for 3D chips, advances in wafer probing, 3D design-for-test architectures and ongoing IEEE P1838 standardization efforts for test access, and 3D test cost modeling and test-flow selection.

    Intended Audience: Test and design-for-test engineers and their managers; researchers, university professors, and students; test methodology developers; test-automation tool developers.

  6. DELAY TEST: CONCEPTS, THEORY AND RECENT TRENDS

    Suriyaprakash NATARAJAN, Arani SINHA


    This tutorial covers fundamental concepts, recent ideas and industry practices on validating and testing integrated circuits for speed failures. Main areas covered are: (a) defects and marginalities such as crosstalk, voltage droop, multiple-input switching and charge-sharing that result in speed failures, (b) delay fault models and fault sensitization conditions, © classical and advanced metrics to measure delay test quality and methods to improve them, (d) design-for-test to facilitate application of delay tests, (e) algorithms for test generation, fault simulation and diagnosis, including cell-aware and those targeting memory shadow and time borrowing logic, and (g) applications in post-silicon validation, speed binning and in-field reliability using industry case studies.

    Intended Audience: The tutorial provides a broad overview of delay test and discusses fundamental concepts and current practices. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test.

  7. HIERARCHICAL TEST FOR TODAY’s SoC and IoT

    Yervant ZORIAN


    Today’s SoC and IoT design teams, use heterogeneous IP blocks from numerous sources, and multi-level hierarchical architecture (IPs, cores, subchips, chip). To test such SOCs and IoTs, DFT designers adopt new hierarchical test solutions across heterogeneous cores (memories, logic, AMS and interface IP), in order to support concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500, 1687 and 1149.1, along with intelligent infrastructure IP to help achieve the above advantages.

    Intended Audience: DFT, Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.

  8. TEST, DIAGNOSIS, AND ROOT-CAUSE IDENTIFICATION OF FAILURES FOR BOARDS AND SYSTEMS

    Krishnendu CHAKRABARTY, William EKLOW, Zoe CONROY


    The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as “NTFs” (No Trouble Founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. The problem will only get worse as technology scales and will be compounded as new packaging techniques (SiP, SoC, 3D) extend and expand Moore’s law. This is a problem that must be solved, yet, little effort has been applied up to this point. This tutorial will provide a detailed background on the nature of this problem and will provide DFT, test, and root-cause identification solutions at the board/system level. Practical insights from industry case studies will be highlighted and the presenters will show how recent research results from academia can help solve problems being faced by industry.

    Intended Audience: Board/System designers, Board/system test engineers and their managers, researchers, test methodology developers, and test tool developers.

  9. STATISTICAL ADAPTIVE TEST METHODS TARGETINGZERO DEFECT” IC QUALITY AND RELIABILITY

    Adit SINGH


    Commercial applications continue to demand ever higher IC quality, most notably a “zero defect” target from automotive manufacturers. To cost effectively meet this challenge, innovative new statistical screening techniques improve test effectiveness by first identifying “suspect” parts, that are then more extensively tested, sometimes using tests that specifically target the suspected failure modes. Such adaptive tests exploit statistical correlations in process, performance and defect parameters. This tutorial presents a range of such test methodologies, and illustrates their effectiveness with results from recently published studies on production parts. Commercial tools from new companies in the “Adaptive Test” space are also discussed.

    Intended Audience: Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.

  10. MEMORY TEST & REPAIR IN NANOMETER ERA

    Manuel D’Abreu, Yervant ZORIAN


    Recent growth in content creation has led to an explosion in the use of embedded memories. This tutorial will present a range of memories used, including RAMs and Non-Volatile memories (Flash) and how to ensure detection of today’s defects upon manufacturing and during life time, including process variation and FinFET specific defects. BIST and Repair solutions to address yield optimization, endurance and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today’s SOCs, the tutorial will also cover power management constraints, functional timing implications, test scheduling optimization, and area minimization options.

    Intended Audience: DFT, Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.

  11. COMBINING STRUCTURAL AND FUNCTIONAL TEST APPROACHES ACROSS SYSTEM LEVELS

    Artur JUTMAN, Hans-Joachim WUNDERLICH, Matteo SONZA REORDA


    This tutorial introduces into the best practices, current challenges and advanced techniques of high quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a System on Chip, board or interconnected system) are introduced. The reuse for system test of design for test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area. Test cases are described and discussed.

    Intended Audience: Professionals from IC-level and board-level domains who want to extend their horizon in the complementary test domain learning best practices across the levels and technologies in the areas of board and IC testing, structural and functional test, test at the end of manufacturing and in the field.

  12. FROM DATA TO ACTIONS: APPLICATIONS OF DATA ANALYTICS IN SEMICONDUCTOR MANUFACTURING & TEST

    Haralampos STRATIGOPOULOS, Yiorgos MAKRIS


    This tutorial seeks to elucidate the utility of data analytics in semiconductor manufacturing and test. Relevant concepts from data analytics theory will be introduced and agglomerated with current practice, showcasing their effectiveness on actual case studies with industrial data. A comprehensive survey of the relevant literature (including but not limited to the presenters’ own work) will be provided, organized around four themes: (i) Test cost reduction through replacement of expensive tests by inexpensive alternatives and/or elimination of superfluous tests, either statically or adaptively during test application, (ii) Pre-deployment evaluation of candidate test methods through probabilistic test metrics, (iii) Post-production performance calibration through cost-effective knob tuning, and (iv) Yield learning and process monitoring through analysis of process variation impact on wafer-level spatial correlation.

    Intended Audience: This tutorial is intended for (i) process and test engineers who wish to understand the utility of data analytics in their practice, (ii) graduate students/faculty/researchers who wish to familiarize with the state-of-the-art and conduct research in this domain, and (iii) data analytics experts who wish to apply their expertise on semiconductor manufacturing data.