ITC 2015 Workshops – 2016 Workshop Information Coming Summer 2016

In 2015 there were three workshops running right after the main conference. Watch this space for information on 2016 workshops when it becomes available.

The 2015 Workshops were:

3D-TEST: 6th IEEE International Workshop on Testing Three Dimensional Stacked ICs

2015 3D-Test Workshop Program Now Available

Click here for the program of the 3D-Test Workshop for 2015.

Scope: The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. Topics to include:

Defect due to wafer thinning Defect in intra-stack interconnects
Failure Analysis for 3D-SICs Known-Good Dies / stack testing
Reliability for 3D-SICs Standardization for 3D testing
Test cost modeling for 3D-SICs DfT Architecture for 3D-SICs

General Chair: Yervant Zorian,
Program Chair: Erik Jan Marinissen,
3D-Test Home Page:

TVHSAC: 4th IEEE International Workshop Test & Validation of High Speed Analog Circuits

Scope: Today, we are in the internet-of-things (IoT) era – an era of sensors and components connected across a high speed communication infrastructure with analysis by massive data center “clouds”, the building blocks are systems-on-chip (SoC) integrated with several diverse IP modules. Analog and mixed-signal (AMS) circuits form many of the critical components of SoCs that push the boundaries of high bandwidth and low power. AMS circuits, such as phase-locked loops, sensors, amplifiers, wired and wireless interfaces are often embedded in a chip with limited controlability to access them.

The demand for high performance, high bandwidth and low power has resulted in AMS designs operating at their margins. The unimaginable levels of integration has come at the cost of increased manufacturing process variations, vulnerability to defects, and accelerated device aging. In this scenario, verifying and validating AMS circuits, which are particularly sensitive to variations and electrical noise, in both pre-silicon and post-silicon phases, has become a great challenge. Effective diagnosis to improve AMS yield, and manufacturing test methods to detect catastrophic faults and unexpected process excursions that have contributed to increased AMS-related customer returns are a necessity. Further, sensitive AMS circuits such as those used in health and automotive products need to have a high degree of in-field reliability requiring fault tolerance and adaptive operation. Since most AMS circuits are often the gateways to a SoC, ensuring their secure design is of vital importance to prevent compromising the security of the chip. These quality objectives should be met under market requirements of aggressively low product cost and product cycle time.

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems.

The scope of the workshop includes, but not limited to:

Analog DFT and test methods High-Speed PLL Test and Characterization
ATE for high speed analog measurement SERDES test and characterization
Self-Healing & Self-Calibration Techniques On-die high speed sensors and test structures

General Chair: Suriya Natarajan,
Program Chair: Manuel Barragan,
TVHSAC Home Page:

DATA: IEEE Workshop on Defect and Adaptive Test Analysis

Scope:Every year, we revisit the scope of the DATA workshop to capture emerging issues, but the common theme has always been DATA, specifically, semiconductor test and yield data. We need to not only measure and collect data, but also to process the data appropriately for yield analysis. The data can come from variety of sources, including test sort & fail bins, in-line defect inspection, test measurement, memory bitmapping, scan diagnosis, and physical failure analysis. There is a need to aggregate, overlay, and cross correlate the data from these various sources in a way that allows efficient yield learning and enables a speedy production ramp. Workship topics are:

Data storage and security Analog fault modeling & coverage
Test data analysis Adaptive test for product engineers
Data mining methods for test data processing High/low voltage and stress testing
Yield learning and analysis I/O test, tuning, and adjustment

General Chair: Arani Sinha,
Program Chair: Jennifer Dworak ,

DATA Home Page: