Workshops

ITC 2014 Workshops

In 2014 there are two workshops running right after the main conference. You can register for a workshop along with your ITC registration.

The 2014 Workshops are:

3D-TEST: 5th IEEE International Workshop on Testing Three Dimensional Stacked ICs

Scope: The second 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. Topics to include:

Defect due to wafer thinningDefect in intra-stack interconnectsDFT Architecture for 3D-SICs
Failure Analysis for 3D-SICs Known-Good Dies / stack testing Reliability for 3D-SICs
Standardization for 3D testing Test cost modeling for 3D-SICs Test flow optimization for 3D-SICs
Tester Architecture for 3D-SICs TSV test, redundancy, and repair

General Chair: Yervant Zorian, zorian@synopsys.com
Program Chair: Erik Jan Marinissen, erik.jan.marinissen@imec.be
3D-Test Home Page: http://3dtest.tttc-events.org/

DATA: IEEE Workshop on Defects, Adaptive Test, and Data Analysis

Scope: It’s all about the DATA. Everything we do in test relies on data. We use data to identify our good parts, our bad parts, and our weak parts. We manipulate test data to detect outliers and reliability risks. We use data to control and adjust future testing. We also use data to record the full history of wafer lots and to track baseline production changes. And of course we have to collect all that data, store it, analyze it, secure it, and syndicate it to authorized consumers. The DATA-2014 will feature papers in the area of semiconductor test data management, analysis, and syndication. Of particular interest are innovations and advancements in: application of “Big Data” analysis techniques to test data, semiconductor test data acquisition methods, data storage and retrieval, security and syndication, analysis methods including data mining, and implementation of adaptive test. The IEEE International Workshop on Defect & Adaptive Test Analysis (DATA 2014) is aimed at addressing the above issues. Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

Data storage and security Analog fault modeling & coverage Test data analysis
Adaptive test for product engineers Data mining methods for test data processing High/low voltage and stress testing
Yield learning and analysis I/O test, tuning, and adjustment Defect coverage and Metrics
Product and project case studies Advanced DPPM reduction techniques Fault localization and diagnosis

General Chair: Arani Sinha, Arani.Sinha@intel.com
Program Chair: Jeff Roehr, JLRoehr@TI.com

DATA Home Page: http://data.tttc-events.org/