Workshops

ITC 2015 Workshops

In 2015 there are three workshops running right after the main conference. You can register for a workshop along with your ITC registration.

The 2015 Workshops are:

3D-TEST: 6th IEEE International Workshop on Testing Three Dimensional Stacked ICs

Scope: The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. Topics to include:

Defect due to wafer thinning Defect in intra-stack interconnects
Failure Analysis for 3D-SICs Known-Good Dies / stack testing
Reliability for 3D-SICs Standardization for 3D testing
Test cost modeling for 3D-SICs DfT Architecture for 3D-SICs

General Chair: Yervant Zorian, zorian@synopsys.com
Program Chair: Erik Jan Marinissen, erik.jan.marinissen@imec.be
3D-Test Home Page: http://3dtest.tttc-events.org/

TVHSAC: 4th IEEE International Workshop Test & Validation of High Speed Analog Circuits

Scope: Demand for higher bandwidths never lets up in the world of communication and networks. While we struggle today to make 40Gbps line-rates a reality, plans are already afoot for 400Gbps. Similarly in wireless communications, 60Ghz is coming on-line today, but designers are already planning the next few generations up to Thz. What is high-speed? It clearly depends: on the medium of transmission, on power constraints, on process technology, on link parallelism, on cost and quality requirements and on the electrical and thermal environment of operation. These constraints define a multi-dimensional box that designers are placed in and asked to provide the highest bandwidth they can, inside a room whose walls seem constantly to move inwards. A lot of the functionality is increasingly analog with strict standards regulating their design and use. And it is a race with no end in sight. The IEEE Workshop on Test and Validation of High Speed Analog Circuits is designed to address a big aspect of this race: cost and quality. Increasing speed has given rise to a spike in complexity of analog circuits. This has been further stressed by the need for integrating with digital functionality in SOCs. Defect coverage alone is no longer sufficient to qualify a die. We need parametric coverage, as early in the manufacturing flow, as possible. This workshop addresses defect and parametric coverage of all analog circuits involved in making high bandwidth communications a reality. The scope of the workshop includes, but not limited to:

Analog DFT and test methods High-Speed PLL Test and Characterization
ATE for high speed analog measurement SERDES test and characterization
Self-Healing & Self-Calibration Techniques On-die high speed sensors and test structures

General Chair: Suriya Natarajan, suriyaprakash.natarajan@intel.com
Program Chair: Manuel Barragan, manuel.barragan@imag.fr
TVHSAC Home Page: http://tima.imag.fr/conferences/tvhsac/

DATA: IEEE Workshop on Defect andAdaptive Test Analysis

Scope:Every year, we revisit the scope of the DATA workshop to capture emerging issues, but the common theme has always been DATA, specifically, semiconductor test and yield data. We need to not only measure and collect data, but also to process the data appropriately for yield analysis. The data can come from variety of sources, including test sort & fail bins, in-line defect inspection, test measurement, memory bitmapping, scan diagnosis, and physical failure analysis. There is a need to aggregate, overlay, and cross correlate the data from these various sources in a way that allows efficient yield learning and enables a speedy production ramp. Workship topics are:

Data storage and security Analog fault modeling & coverage
Test data analysis Adaptive test for product engineers
Data mining methods for test data processing High/low voltage and stress testing
Yield learning and analysis I/O test, tuning, and adjustment

General Chair: Arani Sinha, Arani.Sinha@intel.com
Program Chair: Jennifer Dworak , JDworak@lyle.smu.edu

DATA Home Page: http://data.tttc-events.org/