Three workshops are available towards the end of ITC test week.
With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable and secure operation of electronics in safety- critical, enterprise servers and cloud computing domains is still a major challenge.
While traditionally design time and test time solutions were supposed to guarantee the in-field dependability and security of electronic systems, due to complex interaction of runtime effects from running workload and environment, there is a great need for a holistic approach for silicon lifecycle management, spanning from design time to in-field monitoring and adaptation. Therefore, the solutions for lifecycle management should include various sensors and monitors embedded in different levels of the design stack, access mechanisms and standards for such on-chip and in- system sensor network, as well as data analytics on the edge and in the cloud. The SLM Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.
IEEE Automotive Reliability and Test & Safety Workshop 2024
The ARTS workshop focuses exclusively on test, reliability and Safety of automotive and mission-critical electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operations under different environmental conditions.
With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable operation of electronics in safety-critical domains is still a major challenge. This edition of the ARTS Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.
“Top Picks in Test and Reliability” is a workshop that collects and presents the most impactful publications in the past 6 years in the areas of VLSI test and reliability. For this first inaugural edition of the workshop, all articles in conferences and journals published from 2017 until the submission deadline are eligible. The Workshop will take place in conjunction with the 2023 IEEE International Test Conference.
We accept self-nominations by authors in the form of a 2-page letter. On the first page, the authors should summarize the key ideas and contributions of the publication, and, on a second page, the description of the influence on ongoing research in the field and the potential of making a positive impact for the long term in the microelectronics industry. Submitted publications will be reviewed by a committee of renowned experts in the field and will be shortlisted. An author of each shortlisted publication is required to attend the workshop in-person to present the publication, showcasing its influence and impact. The same committee (or a subset of it) will be also present at the workshop to select a final list of Top Picks which will be then invited for submission to an IEEE Design & Test special issue. The submission should not repeat or reword the original publication. It should be an extended version with new material. Alternatively, it can be a de novo review or tutorial article on the general topic of the original publication. It may have an author list that is different compared to the original publication. Link to the submission website: https://easychair.org/conferences/?conf=tptr2024
“The 3D & Chiplet TEST Workshop” focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs, including systems-in-package (SiP), package-on-package (PoP), 3D-Stacks based on through-silicon vias (TSVs), micro-bumps, and/or interposers.
While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing and repairing such products.
The 3D & Chiplet TEST Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.
Silicon Lifecycle Management (SLM): http://slm.tttc-events.org/
Top Picks in Test and Reliability (TPTR): tptr24.tttc-events.org
3D & Chiplet TEST Workshop (tttc-vts.org)
