Tuesday Plenary Keynote

Shankar Krishnamoorthy

General Manager, EDA Group & Corporate Staff at Synopsys Inc

Title:  Test and Telemetry in the Age of Pervasive AI

Biography:  Shankar Krishnamoorthy leads the Technology & Product Development Group (TPG), which is responsible for researching, creating, and delivering innovative, scalable, high-quality products and platforms for Synopsys across design, verification, signoff, test, silicon lifecycle management (SLM), TCAD, manufacturing domains for digital, analog, and mixed-signal designs, hardware-assisted verification, and systems software.

Prior to leading TPG, Shankar held other executive positions at Synopsys, including GM of the Electronic Design Automation Group and Digital Design Group and Senior Vice President of the Digital Implementation Group. Under his leadership, Synopsys has delivered several ground-breaking technologies enabling semiconductor designers to achieve the most optimum power, performance, area, cost, and time to market on their most advanced products. Before rejoining Synopsys in 2017, Shankar served as GM of the IC Design Solutions Division at Mentor Graphics. He joined Mentor in 2007 with the acquisition of Sierra Design Automation, where he was founder and CTO. Prior to Sierra Design, Shankar led Synopsys’ physical synthesis and logic synthesis R&D organizations.

Shankar received his M.S. in Computer Science from the University of Texas, Austin, and his bachelor’s degree in Computer Science from the Indian Institute of Technology, Bombay.

Abstract:  The proliferation of silicon content in the age of pervasive AI means that test and telemetry is more important than ever in the development of software-defined systems. This silicon to systems approach is also driving multi-die innovation to solve the challenges around scaling and complexity as well as safety and reliability. In this keynote Shankar will also share his thoughts on the future of semiconductor test and discuss how AI will continue to shape and streamline Synopsys’ innovative test and telemetry solutions over the next decade.

Tuesday Visionary Talk

Sriram Sankar

Director, Infrastructure at Meta

Title:  Herding Llamas:  Testing for AI at Hyperscale

Biography:  Sriram Sankar is a Director of Engineering at Meta, where he leads teams that are responsible for the entire lifecycle of Meta’s AI Silicon at Scale. Previously, Sriram led teams that are responsible for the Hardware Health and Availability of the Global Compute/Storage/AI server fleet at Meta.

Prior to Meta, Sriram led the engineering organization responsible for server and data center infrastructure at GoDaddy. In his previous role at Microsoft, Sriram was responsible for the technical strategy and architecture of Microsoft’s global data center footprint. Sriram was also a primary member of the Cloud Server Infrastructure team, developing the next-gen server and datacenter hardware for Microsoft’s cloud services infrastructure. Sriram has a Masters and PhD degree in Computer Science from the University of Virginia. He also has 10+ granted patents, 50+ publications, and is a keynote speaker at top conferences. In recent years, his team’s work on Silent Data Corruptions has been featured in several media articles, including the NY Times, HPC Wire, Register, Forbes, SemiEngineering, and other prominent technical blogs.

Abstract:  The talk will share insights from Meta’s experience in a hyperscale environment, highlighting the testing methodologies used in production. The talk will cover work on Silent Data Corruptions, and the efforts made to detect and remediate this issue at scale. This work from Meta has been featured in numerous media articles and has shifted industry perspectives on Silent Data Corruptions.

The talk will also explore the challenges of deploying and testing large AI clusters and how Meta successfully delivered the Llama3 Herd of models. Finally, the talk will preview the challenges ahead in the MTIA space, Meta’s Training and Inference Accelerators. Designing and deploying silicon for AI applications requires pushing the limits on every phase of the silicon lifecycle. The talk will conclude with a call to action, highlighting specific areas that are relevant to emerging AI applications at scale.

Tuesday Special Event (1:30 PM)

Fireside chat on Allyship and DEI

Ruth Cotter

Sr Vice President, Marketing, Communications and HR, AMD

Biography:  Ruth Cotter is senior vice president at AMD where she oversees Marketing, Communications and Human Resources. In her role, Cotter is responsible for unifying and aligning the AMD brand and people for success. With more than 25 years of experience, Cotter’s leadership has been instrumental in helping the company scale during hypergrowth and is guided by thoughtful policy and planning.

With record revenue growth over the past five years, she supported scaling marketing programs and increasing brand awareness through its “together we advance” brand, strengthened thought leadership positioning of AMD Executive Team and increased engagement and commitment among global AMDers. She has led the HR team during a period when AMD doubled the size of its workforce with a strong focus on diversity and inclusion through improved company policies, benefits and community engagement. In her previous role, Ruth oversaw investor relations where she led a proactive investor outreach campaign that resulted in AMD being among the best performing stocks on the S&P 500 and winner of 2023 Institutional Investor Magazine Most Honored Large Cap Semiconductor Company.

Cotter also successfully led the AMD Integration Planning Office following the company’s acquisition of Xilinx in 2022. Since 2020, she’s led a multi-disciplinary COVID-19 team, ensuring employee safety and support for AMD employees. This team also drives the strategy and execution for transitioning employees back to the office while continuing to support workplace flexibility and employee wellbeing.

Cotter is Executive Sponsor of the AMD PRIDE and Women’s Forum Employee Resource Groups. She serves on the Global Semiconductor Alliance (GSA) Women’s Leadership Council where she is active in initiatives that provide inspiration and sponsorship for the next generation of women leaders. She was honored as the Irish Technology Leadership Group (ITLG) 2023 Distinguished Leader and was named a 2023 Top 100 HR and Communication Professionals by National Diversity Council.

Nitza Basoco

Technology and Market Strategist, Teradyne

Biography: Nitza Basoco is the Technology and Market Strategist in the Semiconductor Test Division at Teradyne, focusing on start-ups, emerging companies and hyperscalers.  With over 23 years of experience in the semiconductor industry, Nitza is a proven leader with deep technical expertise in bringing emerging technologies to market. 

Prior to Teradyne, Nitza was the Vice President of Business Development at proteanTecs, responsible for their partnership strategy and value-add ecosystem growth.  Before that, she was Vice President of Operations of Synaptics and held various leadership positions at MaxLinear. Her time as a principal test development engineer (TDE) at Broadcom provided vital experience in semiconductor test.

 

Nitza holds a Master of Engineering and a Bachelor of Science degree from MIT and an Executive Master of Business Administration (EMBA) from Quantic School of Business and Technology.  She is an active volunteer with the Global Semiconductor Alliance Women’s Leadership Initiative (GSA WLI), a mentor in the GSA Women in Hardware program (WHM) and on the National Academy Foundation (NAF) Advisory Board of the Compton Unified School District. 

Wednesday Keynote

Steve Hesley

Corporate Vice President at AMD

Title:  The Future of Computing Depends on You

Biography:  Steve is a Corporate Vice President at AMD whose focus is on scalable, quality systems. Steve has 30+ years of experience in design and product engineering.

Steve has been responsible in the last several years for a cross functional team that addresses key quality concerns across AMD server products from development to validation and manufacturing ramp to customer enablement and sustaining support and drives corrective action into AMD processes as well as industry standards, research, and vendor collaborations. His additional responsibilities include RAS architecture, Design for Test and Debug IP and CAD, and the on-chip control and data planes of the Infinity Fabric.

Abstract:  Computing is expanding at an incredible rate and permeating ever more aspects of everyday life.   There are multiple challenges to this expansion that must be addressed to maintain the public trust through this expansion.  Innovation and collaboration are needed in Design for Test (DFT) and Reliability, Availability, and Serviceability (RAS).   Steve will share examples from AMD while leading a cross functional team addressing these issues.    He will share a vision for the DFT and RAS community to approach these challenges. 

Thursday Keynote

Mike Slessor

Chief Executive Officer at FormFactor Inc.

Title:  From the Shadows to the Spotlight – Probe’s Role in Enabling Electronics Industry Innovation

Biography: Mike Slessor has served as the President and Chief Executive Officer of FormFactor since 2014, and as a director since 2013. Mike served as President from 2013 to 2014, and as Senior Vice President and General Manager, MicroProbe Product Group from 2012 to 2013.

Before joining FormFactor, he was President and Chief Executive Officer of MicroProbe from 2008 through the 2012 closing of FormFactor’s acquisition of MicroProbe. Prior to joining MicroProbe, he held various management, product-marketing, and applications-engineering positions in the semiconductor industry, primarily with KLA. Mike received his Ph.D. in aeronautics and physics from the California Institute of Technology and his B.A.Sc. in engineering physics from the University of British Columbia.

Abstract:  Once thought of as a relatively simple test insertion, probe today is anything but simple. Increasing performance and capability has been driven by probe’s ascent to a key enabler for economically-viable semiconductor manufacturing at the leading edge, especially for advanced-packaging architectures that rely on 2.5-D and 3-D stacking of chiplets.  We will explore the factors driving increased performance and capability in probe applications from high-bandwidth-memory DRAM, through high-performance-compute xPUs, to even co-packaged electro-optical silicon photonics.

To keep pace with accelerating industry requirements in both test intensity and test complexity, there have been significant advancements in the products and technologies that test suppliers deliver in each of these applications.  For example, a state-of-the-art DRAM test cell tests every die on the wafer simultaneously, through a probe-card interface that contains well over 100,000 individual probes, each with a cross-sectional area comparable to a human hair and carrying an amp of current at relatively high frequencies, all while absorbing up to a hundred microns of cross-wafer topography across a hundred-degree temperature range. To meet these astounding performance requirements with viable business models, there have been equally significant changes in the test-industry supplier landscape.

As we look to the future, it’s clear that this torrid pace of innovation and change will continue.  The only way we will successfully continue to meet these requirements and enable the rapid advancements in the electronics industry is to ensure effective and seamless collaboration across the community of test suppliers and our customers.